Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing
نویسندگان
چکیده
This paper extends the model in [4] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures’ impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a defect level of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.
منابع مشابه
At-Speed BIST for Board-Level Interconnect
This article describes a novel Boundary Scan-like Built-In Self-Test (BIST) conception for autonomous at-speed testing and diagnosis of interconnect. It is based on recently proposed very efficient design of test pattern generation and response analysis hardware, which allows detection and diagnosis of both static and dynamic faults upon interconnects between chips in a multi-chip environment. ...
متن کاملExploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors
Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making design simpler, it introduces extra overheads by way of inter-cluster communication. This communication ...
متن کاملFailure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
SEMATECH has sponsored a " Test Method Evaluation " study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper presents the results of the failure analysis portion of that project. The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including " IDDq-only " failures...
متن کاملLI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects∗ KRISHNA SEKAR AND SUJIT DEY
For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to ...
متن کاملDo humans produce the speed-accuracy trade-off that maximizes reward rate?
In this paper we investigate trade-offs between speed and accuracy that are produced by humans when confronted with a sequence of choices between two alternatives. We assume that the choice process is described by the drift diffusion model, in which the speed-accuracy trade-off is primarily controlled by the value of the decision threshold. We test the hypothesis that participants choose the de...
متن کامل